One of the operation modes that are capable of consecutively performing high-speed reading operation in a semiconductor memory device is a burst mode. A burst mode is a mode that outputs memory data at addresses consecutive from an address input from external to the memory device as an origin. The number of consecutive output bits has 2 bits, 4 bits, 8 bits or the like designated. In the burst mode, there is a method in which addresses consecutive to an external address are internally generated on the basis of the external address, and the generated addresses are decoded to output memory data. In this method, an internal memory cell array is divided into a memory cell array at an odd-numbered address side and a memory array at an even-numbered address side. In the burst mode, addresses from which the lowest-order bit is eliminated are supplied to column decoders of the odd-numbered address side memory cell array and the even-numbered address side memory cell array with respect to the address given from the external or the addresses internally generated. The application of the above circuit structure makes it possible to consecutively always read out the memory data of 2 bits. This is called a “2-bit prefetch circuit” which is capable of performing high-speed burst read.
FIG. 8 shows an example of a 2-bit prefetch circuit of a conventional SDRAM 900 in Patent document 1 (Patent Document 1: JP 10-340579A (paragraphs 0006 to 0010, and FIG. 13)). In this example, the memory cell array is divided into an odd-numbered address memory cell array 910 and an even-numbered address memory cell array 920. Then, address predecoders 911, 921 and address main decoders 912, 922 are provided in the respective memory cell arrays 910 and 920. In addition, the outputs of the respective memory cell arrays 910 and 920 are amplified by data bus amplifiers 913 and 923.
The SDRAM 900 operates in synchronism with a clock 901 supplied from a system side. Accordingly, a command signal 902 is latched in a command latch decoder 932, and an address signal 903 (10 bits of a0 to a9 in this example) is latched in an address buffer 933 at a timing of a clock 931 outputted from a clock buffer 930 that takes in the clock 901. Then, the address signals a3 to a9 from the address buffer 933 are latched in an address latch 938 at a timing of an address latch clock 935 that is generated by the command latch decoder 932. Also, the address signals a1 and a2 are latched in an address latch counter 939 according to the same clock 935.
The address signals a3 to a9 are supplied to the odd- and even-numbered address predecoders 911 and 921 as they are. On the other hand, the addresses a1 and a2 are supplied to the odd-numbered address predecoder 911 as they are. Also, a latch address 944 of the addresses a1 and a2 or a new shift address 948 whose address value increases by 1 through an address+1 arithmetic circuit 946 is supplied to the even-numbered address predecoder 921 according to a value of a lowest-order address a0, that is, according to an odd number or an even number. The reason why the shift address 948 is necessary is that since the memory data at a given column address and memory data at a column address subsequent to the given address are consecutively outputted, it is necessary to generate the subsequent address with respect to the given column address.
In other words, the shift address 948 that has been subjected to address+1 processing by the address+1 arithmetic circuit 946 is generated with respect to the given column address, and the column address (a2, a1) that is supplied to the even-numbered-side decoder changes in response to the lowest-order bit a0 of the given address being 0 (even-numbered address) and 1 (odd-numbered address). Similarly, the order of latching the outputs of the data bus amplifiers 913 and 923 to output data latch circuits 916 and 926 changes in response to the lowest-order bit a0 being 0 or 1.
When it is assumed that the given address is (a2, a1, a0)=(0, 0, 0), a first address becomes (0, 0, 0), and a second address becomes (0,1,0). In this situation, because the lowest-order address a0 is “0”, data that is initially read is data in the even-numbered memory cell array, and data that is subsequently read is data in the odd-numbered memory cell array. Accordingly, (a2, a1)=(0, 0) needs to be supplied to both of the odd-numbered-side decoder and the even-numbered-side decoder. Similarly, when it is assumed that the given address is (a2, a1, a0)=(0, 0, 1), the first address is (0, 0, 1), and the second address is (0, 1, 0). In this situation, because the lowest-order address a0 is “1”, data that is initially read is data in the odd-numbered memory cell array, and data that is subsequently read is data in the even-numbered memory cell array. Accordingly, it is necessary to supply (a2, a1)=(0, 0) to the odd-numbered-side decoder and supply (a2, a1)=(0, 1) that has been subjected to +1 to the even-numbered-side decoder.
The operation of data output will now be described. In the case where the external address is the lowest-order address a0=0 (even-numbered address), the even-numbered memory data 924 that has been outputted from the even-numbered data bus amplifier 923 is latched in the output data latch circuit 916 at a timing of a clock 956. Then, the odd-numbered memory data 914 that has been outputted from the odd-numbered data bus amplifier 913 is latched in the output data latch circuit 926 at a timing of a clock 957. Then, data is consecutively outputted in the order of even and odd from the output data latch circuits 916 and 926.
On the other hand, in the case where the external address is the lowest-order address a0=1 (odd-numbered address), the odd-numbered memory data 914 is latched in the output data latch circuit 916 at a timing of the clock 956, and the even-numbered memory data 924 is latched in the output data latch circuit 926 at a timing of the clock 957, respectively. Then, data is consecutively outputted in the order of even and odd from the output data latch circuits 916 and 926.
However, in Patent Document 1, no operation of the redundancy function is disclosed. Therefore, it is assumed that a circuit is constituted such that a redundancy judge circuit 970 (a circuit having an even-numbered-side judgment section 971 and an odd-numbered-side judgment section 972 which judges an address that needs to be relieved) is added to the circuit shown in FIG. 8, and the latch address 944 that does not pass through the address+1 arithmetic circuit 946 is supplied to the redundancy judge circuit 970 to conduct redundancy comparison.
When the address that is supplied from the external is (a2, a1, a0)=(0, 0, 1), (a2, a1)=(0, 0) is supplied to the odd-numbered address predecoder 911, and (a2, a1)=(0, 1) that has been subjected to address+1 processing is supplied to the even-numbered address predecoder 921, respectively. Then, data is consecutively read from the memory cell array in the order of consecutive column addresses (0, 0, 1) and (0, 1, 0). However, because the column address (a2, a1)=(0, 0) of the latch address 944 that is not subjected to address+1 processing is supplied to both of the odd-numbered-side judgment section 972 and the even-numbered-side judgment section 971 of the redundancy judge circuit 970, the redundancy judgment of data is consecutively conducted in the reverse order of the consecutive column addresses (0, 0, 1) and (0, 0, 0). As a result, there occurs a situation in which there are addresses that do not coincide with each other at the time of decoding the even-numbered address.
Therefore, there occurs a situation in which the addresses that are supplied to the memory cell array 920 and the even-numbered-side judgment section 971 of the redundancy judge circuit 970 do not coincide with each other, and there is a fear that the redundancy comparison of the even bit line is not precisely conducted. This is a problem. That is, in the case where a start address is odd, the even-numbered internal address is subjected to address+1, and a 2-bit prefetch operation is conducted, to thereby incorporate the non-corresponding redundancy judge circuit 970 into a circuit that realizes the same access time as that of the even start at the time of the odd start. In this case, there occurs a situation in which the order of the addresses to be read is reversed, and the redundancy judgment is not precisely conducted when the external address odd-starts, which is also a problem.
In addition, when a circuit is constituted such that the shift address 948 that has passed through the address+1 arithmetic circuit 946 is supplied to the even-numbered judgment section 972 of the redundancy judge circuit 970 at the time of even-starting the external address, it is possible to normally conduct 2-bit prefetch operation. However, the SDRAM 900 normally has a plurality of banks, and the address+1 arithmetic circuit 946 needs to be provided for each of the banks while the redundancy judge circuit 970 is provided commonly to the respective banks.
Accordingly, when the address+1 arithmetic circuits 946 provided in each of the banks are going to be shared by a single redundancy judge circuit 970, it is necessary that the respective shift addresses 948 that are outputted from the plurality of banks are inputted to the redundancy judge circuit. As a result, a circuit for changing over the inputted shift address under control is additionally required, and there is a fear that the circuit size becomes large, which is a problem. Also, there is a fear that the input timing of the shift address that is inputted to the redundancy judge circuit may be off due to a difference in the wiring length from the respective banks, and there is a fear that the circuit size will become large because the circuitry is led around from the respective memory cell circuits to the redundancy judge circuit. This, too, is a problem.
The present invention has been made to eliminate at least one of the above problems with the conventional art. It is desirable to provide a semiconductor memory device and a method of controlling the semiconductor memory device, which are capable of conducting redundancy remedy so as to prevent a fear that the read operation speed becomes low and also capable of reducing the circuit area, even in the semiconductor memory device that conducts the burst read operation due to a 2-bit prefetch operation.